Old UNIX ran all device interrupts on the single CPU. On SMP, interrupt routing is critical. Modern architectures (PCI-based Intel MP spec 1.1, SGI's IRIX, Sun's SBus) support interrupt vectors that can be directed to any CPU.
The danger is . A misbehaving network card at 100Mbps can generate 150,000 interrupts per second. If all interrupts go to one CPU, that CPU is dead. The solution is interrupt coalescing (already in some Ethernet chips) and the use of "kernel threads" for bottom halves, allowing the interrupt dispatcher to merely wake a thread that runs on any CPU.
In 1994, UNIX stands at a paradoxical crossroads. Having vanquished proprietary operating systems from VMS to OS/400, it now faces a crisis born of its own success. The architectures UNIX must run on have fundamentally mutated. The simple, single-issue, in-order scalar processors of the 1980s (e.g., Motorola 68030, Intel 80386) are being replaced by superscalar, out-of-order RISC behemoths (Alpha AXP, MIPS R4000, POWER2, SPARC v9) and, increasingly, Symmetric Multiprocessors (SMPs) with 8, 16, or even 64 CPUs. unix systems for modern architectures -1994- pdf
The traditional UNIX buffer cache—a pool of memory pages used to cache disk blocks—is obsolete on modern architectures for two reasons. First, the virtual memory system can now page directly from the filesystem (using mmap() and clustered pageins). Second, on SMP systems, the buffer cache lock becomes a global bottleneck.
UNIX in 1994 is like a 1960s muscle car with a new fuel-injected engine: powerful but dangerously unstable. The transition to fine-grained locking, 64-bit cleanliness, and interrupt affinity is painful. Many vendors will fail (NeXT, Apollo, perhaps even SVR4 itself). The survivors will be those who treat the kernel not as a monolithic program but as a concurrent data structure problem. Old UNIX ran all device interrupts on the single CPU
Modern RISC CPUs are clocked at 66-200MHz, while DRAM access times hover at 60-80ns. The performance gap—the "memory wall"—is now two orders of magnitude. Consequently, the UNIX kernel’s data structures (process table, buffer cache, vnode/inode tables) must be arranged for L1/L2 cache locality.
This paper examines how UNIX must be—and is being—re-architected for three pillars of the modern (1994) architecture: , non-uniform memory access (NUMA) , and 64-bit addressability . The danger is
By 1994, the 4GB virtual address space of 32-bit UNIX is a cage. Database servers (Oracle 7, Informix OnLine) want to map 64GB of shared memory for buffer pools. The Alpha AXP (OSF/1), UltraSPARC (Solaris 2.4 preview), and MIPS R8000 (IRIX 6) all offer full 64-bit kernels.
The next three years will determine whether UNIX becomes the universal OS for tera-scale computing or fragments into proprietary SMP variants (Windows NT is breathing down our necks). As of April 1994, the smart money is on UNIX—but only if the Berkeley and System V traditions can merge into a truly scalable, modern kernel.